Modern computer systems typically provide some form of virtual memory environment. In an environment of this type, application processes (and in some cases, system processes) access memory using virtual addresses. The computer system is responsible for translating these virtual addresses into physical addresses within the memory of the computer system.
In a typical virtual memory environment, the virtual address space and the physical address space are both divided into fixed size pages. Each virtual address is a combination of a virtual page address and a page offset. Each physical address is a combination of a physical page address and a page offset. Using this system, page addresses may change during address translation, but page offsets remain the same.
The computer system maintains a set of data structures, known as page tables, for each process. The page tables provide a per-process mapping between virtual page addresses and physical page addresses. Translation of a virtual address is accomplished by using the page table to find the physical page address that matches the virtual address being translated. The page offset portion of the virtual address being translated is then added to the physical page address to form the complete physical address.
To provide adequate performance, computer systems using virtual memory typically cache recent translations between virtual and physical page addresses. In most cases, this type of caching is performed by a dedicated cache known as a translation lookaside buffer, or TLB. Use of a TLB dramatically speeds translation because repeated translations involving the same physical page address are performed without the use of page tables.
The performance benefit associated with the use of TLBs has made them indispensable components of virtually all computer systems where virtual memory is used. Still, it is generally the case that traditional TLB implementations have a number of limitations. One limitation is the inability of traditional TLBs to effectively manage systems that include a number of different page types. For example, a computer system may include pages that use linear addressing (where locations in memory are arranged as a linear sequence) and pages that use tiled addressing (where locations in memory are arranged as a number of rows). The same system may also include a number of different sizes for both tiled and linear pages.
Using different page types allows a computer system to optimize performance. Instructions and data that tend to be accessed in a linear fashion may be placed in linear pages. Specialized structures, such as frame buffers, that tend to be accessed on a row-by-row basis, may be placed in tiled pages. In each case, page sizes may be chosen to optimize performance and reduce memory fragmentation.
To use different page types effectively, a TLB must be able to cache translations to each page type. This is problematic because most TLB implementations are geared towards caching only a single type of translation. Effective use of different page types also requires that the TLB be able to separately manage each type. Separate management allows the computer system to prevent the TLB from being monopolized by translations to any particular type of page. Based on the foregoing, it may be appreciated that a need exists for TLB systems that allow for simultaneous use of a range of page types and sizes. A need also exists for systems that allow different page types and sizes to be separately managed.